This invention relates to logic circuitry and, in particular, to buffer circuitry which is compatible with today's field effect transistor random access memories (RAMs).
Commercially available RAMs use output buffers which require more silicon area and/or power than is desirable.
It is desirable, particularly to multiple output memories, to have buffer circuitry which has relatively high speed operation, requires a modest amount of silicon area, and has relatively low power dissipation.